An Architecture Description Language for Embedded Hardware Platforms

Embedded software development relies on various tools - compilers, simulators, execution time estimators - that encapsulate a more-or-less detailed knowledge of the target hardware platform. These tools can be costly to develop and maintain:significant benefits could be expected if they were automatically generated from models expressed in a dedicated modeling language.In contrast with Hardware Description Languages (HDLs), that focus on the internal structure and behavior of an electronic board of chip, Hardware Architecture Description Languages consider hardware as a platform for software execution. Such a platform will be described in terms of low-level programming interface (processor instruction set),resources (processing elements, memory and peripheral devices) and elementary services (arithmetic and logic operations, bus transactions).This paper gives an overview of HARMLESS (Hardware ARchitecture Modeling Language for Embedded Software Simulation), a new domain-specific language for modeling embedded hardware platforms. HARMLESS and its associated tools follow the Model-Driven Engineering philosophy: metamodeling and model transformations have been successfully applied to the automatic generation of processor simulators

An Architecture Description Language for Embedded Hardware Platforms

Embedded software development relies on various tools - compilers, simulators, execution time estimators - that encapsulate a more-or-less detailed knowledge of the target hardware platform. These tools can be costly to develop and maintain:significant benefits could be expected if they were automatically generated from models expressed in a dedicated modeling language.In contrast with Hardware Description Languages (HDLs), that focus on the internal structure and behavior of an electronic board of chip, Hardware Architecture Description Languages consider hardware as a platform for software execution. Such a platform will be described in terms of low-level programming interface (processor instruction set),resources (processing elements, memory and peripheral devices) and elementary services (arithmetic and logic operations, bus transactions).This paper gives an overview of HARMLESS (Hardware ARchitecture Modeling Language for Embedded Software Simulation), a new domain-specific language for modeling embedded hardware platforms. HARMLESS and its associated tools follow the Model-Driven Engineering philosophy: metamodeling and model transformations have been successfully applied to the automatic generation of processor simulators

Harmless, a Hardware Architecture Description Language Dedicated to Real-Time Embedded System Simulation

International audienceValidation and Verification of embedded systems through simulation can be conducted at many levels, from the simulation of a high-level application model to the simulation of the actual binary code using an accurate model of the processor. However, for real-time applications, the simulated execution time must be as close as possible to the execution time on the actual platform and in this case the latter gives the closest results. The main drawback of the simulation of application's software using an accurate model of the processor resides in the development of a handwritten simulator which is a difficult and tedious task. This paper presents Harmless, a hardware Architecture Description Language (ADL) that mainly targets real-time embedded systems. Harmless is dedicated to the generation of simulator of the hardware platform to develop and test real-time embedded applications. Compared to existing ADLs, Harmless1) offers a more flexible description of the Instruction Set Architecture (ISA) 2) allows to describe the microarchitecture independently of the ISA to ease its reuse and 3) compares favorably to simulators generated by the existing ADLs toolsets

Design and verification of pipelined circuits with Timed Petri Nets

International audienceA fundamental step in circuit design is the placement of pipeline stages, which can drastically increase the data throughput. Retiming allows optimizing the pipeline with regard to a criterion, for example the required number of registers. This article presents an extension of Timed Petri Net to model synchronous electronic circuits, in order to explore the design space of pipelines. The Timed Petri Nets “à la Ramchandani” with a maximal step firing rule, have notably been used for the modeling of electronic circuits. The RTPN extension, through the reset which model the pipeline stages, and through the delayable transitions which relax some temporal constraints, makes it possible to widen the design space of pipelined systems, and thus to deal with both the retiming and the verification. After a formal definition of this model, we present a method to explore pipelines verifying temporal properties. We apply our approach to a time-multiplexing property allowing the mutualization of operators while minimizing the number of registers

Validation par simulation fine d'une architecture opérationnelle

La validation des systèmes temps réels est une activité indispensable car les conséquences d'une erreur peuvent être catastrophiques. L'approche choisie dans cette thèse se situe en fin du cycle de développement, lorsque le logiciel applicatif est disponible. L'objectif visé est la simulation d'une architecture opérationnelle comprenant une architecture matérielle décrite finement (processeurs et réseaux) et une architecture logicielle connue (indirectement) au travers des programmes exécutables (code applicatif et code système). Une contribution importante de la thèse se situe dans les mécanismes génériques d'extraction d'informations a partir de la simulation "bas niveau" du code assembleur des programmes, pour en déduire des informations "haut niveau" exploitables par le concepteur. L' étude s'est focalisée sur l' étude du flot de données, l'analyse de l'ordonnancement du code final de l'application ainsi que l'analyse de la pile associée à chaque tâche, à travers l'outil ReTiS.The validation of real time systems is an essential activity because consequences of an error could be catastrophic. The approach chosen in this PhD thesis is at the end of the development cycle, when the application software is available, at least important parts. The objective is the simulation of the whole operational architecture, which includes an accurate model of the hardware architecture (processors and network) and a software architecture, indirectly trough the executable code (application code and basic software). An important contribution of this thesis is based on generic mechanisms to extract information from the "low level" simulation of the assembly code in a distributed context, to deduce useful "high level" information to the developer. The work is focused on the data flow analysis, the analysis of the schedule of the final application code and the task's stack analysis, implemented into the ReTiS tool.NANTES-BU Sciences (441092104) / SudocNANTES-Ecole Centrale (441092306) / SudocSudocFranceF

Expressiveness and analysis of Delayable Timed Petri Net

We consider an extension of Timed Petri Nets "à la Ramchandani" where the transitions are partitioned into delayable and non-delayable transitions which has proven to be suitable for the design of synchronous circuits. For this model called Delayable Timed Petri Net (DTPN), the firing delay of a non-delayable transition is strict whereas a delayable transition can miss its firing delay. Since the delays are natural numbers, this model can be studied as a discrete time model. We deal with the expressiveness of DTPN by a comparison with the well known Merlin's Time Petri Net model for which transitions can fire in a time interval. We show that DTPN are strictly more expressive w.r.t. weak timed bisimilarity than Merlin's model under the discretetime semantics. We then deal with the symbolic reachability analysis of DTPN, for which we show the complexity of the successor symbolic state computation to be O(n). In addition, we propose a reduction of the number of edges to explore that preserves the markings and the firing sequences. The symbolic state space exploration is implemented in a prototype tool, which is evaluated on a classical TPN problem and a circuit design application

BEST: a Binary Executable Slicing Tool

International audienceWe describe the implementation of Best, a tool for slicing binary code. We aim to integrate this tool in a WCET estimation framework based on model checking. In this approach, program slicing is used to abstract the program model in order to reduce the state space of the system. In this article, we also report on the results of an evaluation of the efficiency of the abstraction technique

Langage de description d'architecture matérielle pour les systèmes temps réel

Cette thèse propose un nouveau langage de description d'architecture matérielle HARMLESS (Hardware ARchitecture Modeling Language for Embedded Software Simulation). C'est un ADL mixte ; il permet de décrire d'une manière concise les differentes parties d'un processeur : le jeu d'instructions et la structure interne (les composants matériels et le pipeline). L'originalité de HARMLESS est le découplage de la description du jeu d'instructions de la spécification de la micro-architecture (pipeline et concurrences d'accès aux différents composants matériels). L'une des conséquences est de permettre la génération des deux types de simulateurs indépendamment et simultanément : le simulateur de jeu d'instructions (ISS) permettant la vérification fonctionnelle du processeur et le simulateur précis au cycle près (CAS) fournissant des informations temporelles (en nombre de cycles) sur l'exécution de ce dernier. Une autre conséquence est une construction incrémentale de la description : 4 vues séparées permettent de décrire d'une part le jeu d'instructions (3 vues pour la syntaxe, le format binaire et la sémantique) et d'autre part la micro-architecture (une vue) du processeur. Ceci facilite la réutilisation du code sur une nouvelle architecture cible (les jeux d'instructions évoluent beaucoup moins vite que la structure interne d'un processeur). De nombreuses descriptions de processeur ont été réalisées pour prouver la validité des concepts.This thesis aims to propose a new hardware architecture description language HARMLESS (Hardware ARchitecture Modeling Language for Embedded Software Simulation). It is a mixed ADL; it allows to describe concisely the different parts of a processor : instruction set and internal structure (hardware components and pipeline). The originality of HARMLESS is the decoupling of the instruction set description from the micro-architecture description (pipeline and concurrency to access the different hardware devices). One consequence is to allow the generation of two types of simulators independently and simultaneously : the instruction set simulator (ISS) for the functional verification of processors and the cycle accurate simulator (CAS) providing temporal information (in cycles) on the performance of the latter. Another consequence is an incremental construction of description : 4 separate views to describe, one hand the instruction set (3 views for syntax, binary format and semantics) and other hand the processor microarchitecture (one view). This facilitates code reuse on a new target architecture (instruction set progresses much slower than the internal structure of a processor). Many processor descriptions were developed in order to prove the validity of the proposed concepts.NANTES-BU Sciences (441092104) / SudocNANTES-BU Technologie (441092105) / SudocNANTES-Ecole Centrale (441092306) / SudocSudocFranceF